WashU
Introduction to Digital Logic and Computer Design
Fall 2024

Studio 3A


Overview

Studio sessions must be done in small groups of 2-4 people. The group work is an important part of the studio experience. You are not required to work with specific students and may adjust groups next week or when we move to a new room. We expect you to be be respectful and professional in your interactions with your peers.

You should ensure that everyone in your group contributes to and benefits from the work.

Artifacts for this studio

Include an answer to questions in the numbered sections in your submission. Include the relevant section number for each answer, like 1.1.

Chapter 3: Sequential Logic Part 1

Latches & Flip-Flops

Description

Briefly describe the difference between a latch and a flip-flop.

The Edge edge

Why is it important to have an edge-triggered flip-flop and what is required for its construction?

Real D Flip-Flops

Examine the data sheet for the 74175, D-Type Flip-Flop chip: Data Sheet.

  1. How many bits of memory does the chip contain?
  2. How is this chip triggered to change states?
  3. How many pins does this chip have?
  4. Which pin is for power and which for ground?
  5. Explain what the Master Reset does.

JLS D flip-flop model

Open JLS and examine the D flip-flop provided (Remember that Flip-Flops are edge triggered! Use the positive edge triggered flip-flop by picking the Pos-Trig Trigger).

  1. How is the JLS D Flip-Flop different than the 74175?
  2. Use the following to control the D Flip-Flop (Input is the data to store). 
     Input
     0 for 200
     1 for 200
     0 
 end

 Clock
     0 for 60
     1 for 60
     0 for 60
     1 for 60
     0 for 60
     1 for 60
     0 
 end

    Explain the Output of the flip-flop for those inputs.

State Machines

State Representation

Assume a state machine has 5 states. What is the minimum number of bits, $n$, that must be used to build a circuit for the state machine? Explain your reasoning. Why may a designer use a different number of bits?

State Machines Count

Design a state machine that will count from 0 to 3 in binary repeatedly ($0,1,2,3,0,1,2,3,0,1,2,3,\cdots$).

  1. How many bits, $n$, are required to store your state?
  2. Create a state transition table (truth table) that lists all possible states along with the next state of the machine.
  3. What combinational logic is required to obtain the next states for the machine?
  4. Build and simulate the machine in JLS.
    • How many inputs are there to the machine?
    • Instead of using JLS’s clock part, use the signal generator to create a clock signal and cycle through all states of the machine.
  5. Assume we want the machine to count up or down based on an additional input named B. It should count up if B is 0 and count down ($3,2,1,0,3,2,\cdots$) if B is 1.
    • How would the design change if this new input is added?
    • How would the table from part 2 change?

Submission / End-of-class

Discuss your work/findings with TAs/instructors. Submit a copy of the questions with everyone’s name at the top (at least one person should submit it, but it’s ok if everyone does).

Submission Link: Canvas