Overview

Problems 1-6 (and problem 7 description — see below for additional details on problem 7)

Complete problems covering topics from Chapter 3 (use either document format; Clearly show work; Typed work is preferred):

• 260_FL24_Homework3.docx

• 260_FL24_Homework3.pdf

Problem 7: State Diagram and JLS Starter File

Problem 7 is described in the document/pdf, however:

1. You must create a digital logic circuit from basic parts that we’ve covered (any basic gates, or multiplexors, decoders, and flip-flops). You CAN NOT use the JLS state machine tool, the memory block, or the truth table component.
2. You should use the rising edge of the clock to trigger state changes.
3. State updates should be completed in less than 400 units of time.
4. You can rely on some assumptions about inputs:
   1. No more than one input will be active at a time.
   2. One input will be on for every clock cycle unless a Dispense event was expected to happened. Following an expected Dispense, no inputs will be active for one clock cycle.
5. If you’d like to use an online tool to help you draw the state machine, former CSE 132 Head TA Emily Wilson has an updated Finite State Machine Designer online App: https://wilsonem.github.io/fsm/
6. Download and work in this JLS starter: hw3_7d.jls
   • DO NOT change the names of either input or output ports. The Autograder depends on them being named as-is.