Content

The exam covers Modules 4-7, which correspond to Chapters 4-7 of the text book.

Format

  • Paper-based Exam
    • There will be a mix of question styles: multiple choice, fill-in-the-blank, written/short essay/explanation, and problem solving.
  • Expected to take about 60 minutes, but the full 80 minute class time will be given (those with accommodations will have time adjusted proportionally.  2x time = 160 minutes. If possible, coordinate with Disability Resources to have the exam proctored)
  • The exam will focus on concepts and basic understanding. 

Provided Crib Sheet

  • A crib sheet that’s equivalent to Appendix B (machine code representations; covers of book) will be provided.
  • Other RISC-V or CPU specific tables will be provided as needed. (Ex: Tables from chapter 7 that may be needed to describe Data Path)

Crib Sheet / Sage Page (yours)

A crib sheet is allowed, however it must:

  • Be hand written.  No electronic copies / shrinking print / etc.
  • Be less than or equal to half of a single side of letter size paper (8 inches by 5.75 inches of area)
  • Submitted with the exam

Topics

A non-exhaustive list of topics includes:

  • HDL basics
  • Testbench concepts and benefits
  • Verilog
    • Modules
      • Ports (inputs, outputs)
    • Operators
    • logic type
    • Combinational logic and operators in Verilog (always_comb and assign, &, |, ^, ~, etc.)
    • Sequential/synchronous logic (always_ff)
    • Blocking vs. non-blocking assignments (= vs. <=)
  • Synchronous vs. Asynchronous reset
  • Full-Adders
  • Ripple-Carry Adders
  • Two’s Complement Subtraction
  • Basic ALU construction and behavior
  • Basic ROM behavior
  • Basic RAM behavior
  • Register Files and Register File Behavior
  • “Ports” in memory and the concepts of multi-port memories.
  • Memory choices (SRAM vs. DRAM) and their tradeoffs (at a high level)
  • FPGAs: What they are and common facilities/limitations.
  • RISC-V Assembly Language
  • Machine and Assembly Langauge Representations
    • Will focus on basic, integer instructions (ALU opertions, memory operations, branching/jumps).
  • RISC-V model covered in chapters 6 & 7, especially the single-cycle CPU: datapath, control, fetch-decode-execute cycle
  • Multi-cycle CPU behavior and benefits
  • Benefits possible with multi-cycle CPU and pipelines over single-cycle design

Preparation / Problem Styles

The following are a non-exhaustive list of some types of questions that may be present on the exam:

  • Be able to read and identify behavior of basic Verilog
    • module syntax and structure, logic type, operators, if/else, representing constants in binary, hex, and decimal, always_ff procedural blocks and sensitivity lists, case, etc.
  • Be able to create a Verilog module for a given combinational logic description / problem
  • Be able to create a Verilog module for a given state machine description / problem
  • Be able to describe and implement common parts in Verilog, such as full adders, multiplexors, etc.
  • Be able to initialize state variables in Verilog (in response to a a reset)
  • Be able to read/write/create a basic Verilog test bench that applies signals and uses assert to confirm behavior.
  • Be able to describe the net propagation delay through a ripple carry adder.
  • Be able to construct an ALU (gate level or HDL) for basic operations based on a table of “op codes”.
  • Be able to interpret a gate-level or HDL description of an ALU, identify it’s operations, etc.
  • Be able to understand and create basic hardware diagrams of fundamental storage constructs, like ROM, RAM, and Register Files.
  • Be able to understand and create verilog models of fundamental storage constructs, like ROM, RAM, and Register Files.
  • Be able to explain why SRAM is preferable to DRAM for applications, like Register Files, and why DRAM is preferable for others.
  • Be able to explain (at a very high level) how logic is “mapped” to FPGAs, like the iCE40 on the UPDuino.
  • Be able to translate assembly language instructions to machine code (binary) and represent in hexadecimal.
  • Be able to convert machine language (hexadecimal) to symbolic assembly language.
  • Be able to describe the behavior of small snippets of assembly language and/or individual instructions
  • Be able to write small bits of assembly language for a given set of requirements
  • Be able to identify and explain control signals in single-cycle CPU for given instruction
  • Be able to describe benefits of pipelines and multi-cycle CPU
  • Be able to identify concerns about critical paths from CPU diagram

Recommended Review

  • Assigned Reading
  • Posted slides and examples
  • Studio activities
  • Homework
  • Author’s videos and posted “Extra” videos