Exam 1
Content
The exam covers Modules 1-4A, which correspond to Chapters 1-4.4 of the text book. The emphasis (>=90% of the focus) will be on Chapters 1-3.
Format
- Paper-based Exam
- There will be a mix of question styles: multiple choice, fill-in-the-blank, written/short essay/explanation, and problem solving.
- Expected to take about 60 minutes, but the full 80 minute class time will be given (those with accommodations will have time adjusted proportionally. 2x time = 160 minutes. If possible, coordinate with Disability Resources to have the exam proctored)
- The exam will focus on concepts and basic understanding.
Crib Sheet / Sage Page
A crib sheet is allowed, however it must:
- Be hand written. No electronic copies / shrinking print / etc.
- Be less than or equal to half of a single side of letter size paper (8 inches by 5.75 inches of area)
Topics
A non-exhaustive list of topics includes:
- Number Representations
- Binary
- Bytes/Nybbles
- Unsigned
- Sign/Magnitude
- Two’s Complement
- Addition and negation
- Decimal
- Hexadecimal
- Conversions to/from/between different representations
- Binary
- Logic Gates
- All basic gates (AND, OR, NOT, XOR, etc.)
- Truth Tables
- What they are, where/how/why/when to use them.
- Boolean Equations
- Notation / meaning
- Sum-of-Products Form / Minterms
- Translation to Gates or from Gates to Equations
- Basic manipulation and simplification of questions
- Combinational Logic
- Propagation Delay ($t_{pd}$ )
- Contamination Delay ($t_{cd}$)
- Concepts of glitches/hazards
- Simplification via Karnaugh Maps
- Larger Combinational Logic Building Blocks
- Multiplexers
- Decoders
- Sequential Elements
- SR Latch behavior
- D Latch behavior
- D flip flop behavior
- Finite State Machines
- State diagrams
- Next State and Output Tables
- State Encodings
- D Flip Flop Timing Considerations (and impact on Finite State Machines)
- Be able to explain some differnces between VHDL and Verilog
- Given an piece of example code in Verilog or VHDL, be able to describe how it will behave
- Given an piece of example code in Verilog or VHDL, be able to provide a digital logic circuit with equivalent behavior
Preparation / Problem Styles
The following are a non-exhaustive list of some types of questions that may be present on the exam:
- Be able to convert between number representations, like decimal to binary
- Be able to demonstrate basic math (addition and negation) on unsigned and two’s complement numbers
- Be able to translate a problem description into a table suitable for creating a sum-of-products equation
- Be able to translate a table into sum-of-products equations
- Be able to explain the common elements and process needed to convert a problem description into a combinational logic circuit
- Be able to translate a problem description into boolean algebra equations
- Be able to create boolean algebra equations for a given digital logic schematic
- Be able to show the output wave form that will result from given inputs to latches or flip-flops
- Be able to convert truth tables to equations and circuits and circuits to equations and truth tables
- Be able to analyze logic for propagation delay
- Be able to compare/contrast different implementations of combinational circuits in their complexity and potential space use vs. computation time.
- Be able to compare/contrast different choices for state representation
- Be able to describe metastability
Recommended Review
- Assigned Reading
- Posted slides and examples
- Studio activities
- Homework
- Author’s videos and posted “Extra” videos